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Chapter 3: Hardware Description
R
provided with the cores: a simple one-doubleword (DW) register behind the I/O BAR and
a 16 DW memory behind the memory BAR.
To use the provided example implementation for PCI operation:
1.
2.
3.
4.
Load the bitstream onto the ML555 FPGA (see Table 3-37, page 86 ).
Reboot the host computer (without power cycling the ML555 board).
The host BIOS will configure the core for PCI in the design.
Use a configuration utility to verify that the device was configured properly and look
for a device with a Vendor ID of 0x10EE and a Device ID of 0x0050 .
XAPP999 [Ref 7] describes how to build a reference system for the Processor Local Bus
Peripheral Component Interconnect (PLBv46 PCI) core using a MicroBlaze? processor-
based embedded system using the ML555 board.
DDR2 SDRAM SODIMM
The ML555 board contains a 200-pin, small-outline dual in-line memory module
(SODIMM) connector (J2) that supports installation of DDR2 SDRAM SODIMMs of
128 MB, 256 MB, or 512 MB. Dual-rank SODIMMs are not supported. Xilinx provides a
256 MB DDR2-667 SODIMM Micron Semiconductor part number 4HTF3264HY-40E with
the kit. Table 3-5 provides a description of the memory interface signal descriptions,
SODIMM connector pin assignments, and associated FPGA pin assignments. The
SODIMM interface supports customer installation of DDR2-533 and/or DDR2-400
SODIMMs. One of the clock synthesizers must be used to generate the clock frequency for
the SODIMM interface. For most applications, Clock Synthesizer 1 is used for DDR2
memory applications and Clock Synthesizer 2 is used for GTP transceiver applications.
The ML555 board does not support a 72-bit DDR data interface required for parity or error
correction codes (ECC). The speed grade of the FPGA limits the DDR2 memory clock
support to a range of 200-233 MHz or 400-466 million transfers per second. Included on the
CD-ROM is a reference design for the DDR2 memory contained on the ML555. Verilog
source code and a BIT file are included which can be loaded into the FPGA using the
Platform Cable USB download cable and Xilinx iMPACT configuration software. See the
Readme.txt file in the design directory for information about running and implementing
the design.
Characteristics of the DDR2 SDRAM SODIMM (provided with the kit):
?
?
?
?
Organization 32M x 64 bit
Memory clock speed 5 ns/200 MHz using the clock synthesizer
CAS latency 3 or 4 (DDR2-400)
1.8V I/O (Stub-Series Terminated Logic (SSTL_18) compatible)
The data sheet for the DDR2 SDRAM SODIMM kit can be obtained from Micron
Semiconductor at www.micron.com/products/modules . Contact Micron for availability
of other compatible products, including device capacity, clock speeds, and CAS latency
options, in the 200-pin SODIMM form factor.
The ML555 board memory interface design includes on-board 50 Ω termination resistors
to 0.9V, at the FPGA end of the interface, for the 64-bit bidirectional DQ data bus. The
differential DQS signals sourced from the FPGA should use a DIFF_SSTL18_II primitive as
the I/O driver element. The address and control signals have 50 Ω termination resistors to
0.9V at the SODIMM end of the interface. The SODIMM provides a 120 Ω termination
network for the differential clock inputs. On-die termination (ODT) is used to terminate
34
www.xilinx.com
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
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